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femtoclocks? crystal-to-3.3v lvpecl frequency synthesizer ics843242 idt ? / ics ? 3.3v lvpecl frequency synthesizer 1 ics843242ag rev. a november 4, 2008 preliminary g eneral d escription the ics843242 is a 2 differential output lvpecl synthesizer designed to generate ethernet reference clock frequencies and is a member of the hiperclocks? family of high performance clock solutions from idt. using a 31.25mhz or 26.041666mhz, 18pf parallel resonant crystal, the follow-ing frequencies can be generated based on the settings of 4 frequency select pins (sel[a1:a0], sel[b1:b0]): 625mhz, 312.5mhz, 156.25mhz, and 125mhz. the two banks have their own dedicated frequency select pins and can be independently set for the frequencies mentioned above. the ics843242 idt?s 3 rd generation low phase noise vco technology and can achieve 1ps or lower typical rms phase jitter, easily meeting ethernet jitter requirements. the ics843242 is packaged in a small 16-pin tssop package. f eatures ? two 3.3v differential lvpecl output pairs ? using a 31.25mhz or 26.041666 crystal, the two output banks can be independently set for 625mhz, 312.5mhz, 156.25mhz or 125mhz ? crystal oscillator interface ? vco range: 560mhz to 700mhz ? rms phase jitter @ 625mhz (1.875mhz - 20mhz): 0.4ps (typical) ? full 3.3v supply mode ? 0c to 70c ambient operating temperature ? industrial temperature available upon request ? available in both standard (rohs 5) and lead-free (rohs 6) compliant packages hiperclocks? ic s b lock d iagram xtal_in xtal_out qa nqa qb nqb osc phase detector vco 560mhz - 700mhz feedback divider 2 2 0 0 1 0 1 2 (default) 1 0 4 1 1 5 0 0 1 0 1 2 1 0 4 (default) 1 1 5 0 = 20 (default) 1 = 24 sela[0:1} fb_sel selb[0:1} pulldown 0=pullup 1=pulldown 0=pulldown 1=pullup p in a ssignment nqb qb v cco _ b selb1 selb0 v cco _a qa nqa 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 xtal_in xtal_out v ee sela1 sela0 v cc v cca fb_sel ics843242 16-lead tssop 4.4mm x 5.0mm x 0.92mm package body g package top view the preliminary information presented herein represents a product in pre-production. the noted characteristics are based on ini tial product characterization and/or qualification. integrated device technology, incorporated (idt) reserves the right to change any circuitry or specificat ions without notice.
idt ? / ics ? 3.3v lvpecl frequency synthesizer 2 ics843242ag rev. a november 4, 2008 ics843242 femtoclocks? crystal-to-3.3v l vpecl frequency synthesizer preliminary t able 1. p in d escriptions t able 2. p in c haracteristics l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u c n i e c n a t i c a p a c t u p n i 4f p r n w o d l l u p r o t s i s e r n w o d l l u p t u p n i 1 5k r p u l l u p r o t s i s e r p u l l u p t u p n i 1 5k r e b m u ne m a ne p y tn o i t p i r c s e d 2 , 1b q , b q nt u p t u o. s l e v e l e c a f r e t n i l c e p v l . s t u p t u o k c o l c l a i t n e r e f f i d 3v b _ o c c r e w o p. s t u p t u o b q n , b q r o f n i p y l p p u s t u p t u o 41 b l e st u p n ip u l l u p . h g i h = t l u a f e d . b k n a b r o f n i p t c e l e s n o i s i v i d . s l e v e l e c a f r e t n i l t t v l / s o m c v l 50 b l e st u p n in w o d l l u p . w o l = t l u a f e d . b k n a b r o f n i p t c e l e s n o i s i v i d . s l e v e l e c a f r e t n i l t t v l / s o m c v l 6v a _ o c c r e w o p. s t u p t u o a q n , a q r o f n i p y l p p u s t u p t u o 8 , 7a q n , a qt u p t u o. s l e v e l e c a f r e t n i l c e p v l . s t u p t u o k c o l c l a i t n e r e f f i d 9l e s _ b ft u p n in w o d l l u p t e s s i r e d i v i d k c a b d e e f e h t , ) t l u a f e d ( w o l n e h w . t c e l e s e d i v i d k c a b d e e f . 4 2 r o f t e s s i r e d i v i d k c a b d e e f e h t , h g i h n e h w . 0 2 r o f . s l e v e l e c a f r e t n i l t t v l / s o m c v l 0 1v a c c r e w o p. n i p y l p p u s g o l a n a 1 1v c c r e w o p. n i p y l p p u s e r o c 2 10 a l e st u p n ip u l l u p . h g i h = t l u a f e d . a k n a b r o f n i p t c e l e s n o i s i v i d . s l e v e l e c a f r e t n i l t t v l / s o m c v l 3 11 a l e st u p n in w o d l l u p . w o l = t l u a f e d . a k n a b r o f n i p t c e l e s n o i s i v i d . s l e v e l e c a f r e t n i l t t v l / s o m c v l 4 1v e e r e w o p. n i p y l p p u s e v i t a g e n 6 1 , 5 1 , t u o _ l a t x n i _ l a t x t u p n i . t u p t u o e h t s i t u o _ l a t x , t u p n i e h t s i n i _ l a t x . e c a f r e t n i r o t a l l i c s o l a t s y r c : e t o n n w o d l l u p d n a p u l l u p . s e u l a v l a c i p y t r o f , s c i t s i r e t c a r a h c n i p , 2 e l b a t e e s . s r o t s i s e r t u p n i l a n r e t n i o t r e f e r
idt ? / ics ? 3.3v lvpecl frequency synthesizer 3 ics843242ag rev. a november 4, 2008 ics843242 femtoclocks? crystal-to-3.3v l vpecl frequency synthesizer preliminary s t u p n i k c a b d e e f r e d i v i d a k n a b r e d i v i d t u p t u o n / m n o i t a c i l p i t l u m r o t c a f a q n / a q t u p t u o y c n e u q e r f y c n e u q e r f l a t s y r c1 a l e s0 a l e sl e s _ b f 5 2 . 1 30000 21 0 25 2 6 5 2 . 1 30100 22 0 15 . 2 1 3 5 2 . 1 31000 24 5 5 2 . 6 5 1 5 2 . 1 31100 25 4 5 2 1 6 6 6 1 4 0 . 6 20014 21 4 25 2 6 6 6 6 1 4 0 . 6 20114 22 2 15 . 2 1 3 6 6 6 1 4 0 . 6 21014 24 6 5 2 . 6 5 1 6 6 6 1 4 0 . 6 21114 25 8 . 45 2 1 t able 3a. b ank a f requency t able s t u p n i k c a b d e e f r e d i v i d b k n a b r e d i v i d t u p t u o n / m n o i t a c i l p i t l u m r o t c a f b q n / b q t u p t u o y c n e u q e r f y c n e u q e r f l a t s y r c1 a l e s0 a l e sl e s _ b f 5 2 . 1 30000 21 0 25 2 6 5 2 . 1 30100 22 0 15 . 2 1 3 5 2 . 1 31000 24 5 5 2 . 6 5 1 5 2 . 1 31100 25 4 5 2 1 6 6 6 1 4 0 . 6 20014 21 4 25 2 6 6 6 6 1 4 0 . 6 20114 22 2 15 . 2 1 3 6 6 6 1 4 0 . 6 21014 24 6 5 2 . 6 5 1 6 6 6 1 4 0 . 6 21114 25 8 . 45 2 1 t able 3b. b ank b f requency t able t able 3c. o utput b ank c onfiguration s elect f unction t able t able 3d. f eedback d ivider c onfiguration s elect f unction t able s t u p n i v i d _ b fe d i v i d k c a b d e e f 0) t l u a f e d ( 0 2 14 2 s t u p n is t u p t u o 1 a l e s0 a l e sa q 001 01 ) t l u a f e d ( 2 104 115 s t u p n is t u p t u o 1 b l e s0 b l e sb q 001 012 10 ) t l u a f e d ( 4 115
idt ? / ics ? 3.3v lvpecl frequency synthesizer 4 ics843242ag rev. a november 4, 2008 ics843242 femtoclocks? crystal-to-3.3v l vpecl frequency synthesizer preliminary t able 4a. p ower s upply dc c haracteristics , v cc = v cco_a, v cco_b = 3.3v5%, t a = 0c to 70c t able 4b. lvcmos / lvttl dc c haracteristics , v cc = v cco_a = v cco_b = 3.3v5%, t a = 0c to 70c a bsolute m aximum r atings supply voltage, v cc 4.6v inputs, v i -0.5v to v cc + 0.5v outputs, i o contin uous current 50ma surge current 100ma package thermal impedance, ja 92.4c/w (0 mps) storage temperature, t stg -65c to 150c note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only. functional operation of product at these conditions or any conditions beyond those listed in the dc characteristics or ac characteristics is not implied. exposure to absolute maximum rating conditions for ex- tended periods may affect product reliability. l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v c c e g a t l o v y l p p u s e r o c5 3 1 . 33 . 35 6 4 . 3v v a c c e g a t l o v y l p p u s g o l a n av c c 2 1 . 0 ?3 . 3v c c v v , a _ o c c v b _ o c c e g a t l o v y l p p u s t u p t u o5 3 1 . 33 . 35 6 4 . 3v i e e t n e r r u c y l p p u s r e w o p 5 2 1a m i a c c t n e r r u c y l p p u s g o l a n a 2 1a m t able 4c. lvpecl dc c haracteristics , v cc = v cco_a = v cco_b = 3.3v5%, t a = 0c to 70c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v h o 1 e t o n ; e g a t l o v h g i h t u p t u ov x _ o c c 4 . 1 -v x _ o c c 9 . 0 -v v l o 1 e t o n ; e g a t l o v w o l t u p t u ov x _ o c c 0 . 2 -v x _ o c c 7 . 1 -v v g n i w s g n i w s e g a t l o v t u p t u o k a e p - o t - k a e p 6 . 00 . 1v 0 5 h t i w d e t a n i m r e t s t u p t u o : 1 e t o n v o t x _ o c c . v 2 - l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v h i e g a t l o v h g i h t u p n i 2v c c 3 . 0 +v v l i e g a t l o v w o l t u p n i 3 . 0 -8 . 0v i h i t u p n i t n e r r u c h g i h 0 b l e s , 1 a l e s , l e s _ b fv c c v = n i v 5 6 4 . 3 =0 5 1a 1 b l e s , 0 a l e sv c c v = n i v 5 6 4 . 3 =5a i l i t u p n i t n e r r u c w o l 0 b l e s , 1 a l e s , l e s _ b fv c c v , v 5 6 4 . 3 = n i v 0 =5 -a 1 b l e s , 0 a l e sv c c v , v 5 6 4 . 3 = n i v 0 =0 5 1 -a
idt ? / ics ? 3.3v lvpecl frequency synthesizer 5 ics843242ag rev. a november 4, 2008 ics843242 femtoclocks? crystal-to-3.3v l vpecl frequency synthesizer preliminary t able 6. ac c haracteristics , v cc = v cco_a, v cco_b = 3.3v5%, t a = 0c to 70c t able 5. c rystal c haracteristics r e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u n o i t a l l i c s o f o e d o m l a t n e m a d n u f y c n e u q e r f 0 2 = l e s _ b f8 25 2 . 1 35 3z h m 4 2 = l e s _ b f3 3 . 3 26 6 1 4 0 . 6 27 6 1 . 9 2z h m ) r s e ( e c n a t s i s e r s e i r e s t n e l a v i u q e 0 5 e c n a t i c a p a c t n u h s 7f p l e v e l e v i r d 1w m . l a t s y r c t n a n o s e r l e l l a r a p f p 8 1 n a g n i s u d e z i r e t c a r a h c : e t o n l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u f t u o e g n a r y c n e u q e r f t u p t u o 1 = r e d i v i d t u p t u o0 9 40 8 6z h m 2 = r e d i v i d t u p t u o5 4 20 4 3z h m 4 = r e d i v i d t u p t u o5 . 2 2 10 7 1z h m 5 = r e d i v i d t u p t u o8 96 3 1z h m t ) o ( k s3 , 1 e t o n ; w e k s t u p t u o y c n e u q e r f e m a s @ s t u p t u o0 2s p s e i c n e u q e r f t n e r e f f i d @ s t u p t u o0 3s p t ) ? ( t i j ; ) m o d n a r ( r e t t i j e s a h p s m r 2 e t o n ) z h m 0 2 - z h m 5 7 8 . 1 ( z h m 5 2 64 . 0s p ) z h m 0 2 - z h m 5 7 8 . 1 ( z h m 5 . 2 1 35 . 0s p ) z h m 0 2 - z h m 5 7 8 . 1 ( z h m 5 2 . 6 5 15 . 0s p ) z h m 0 2 - z h m 5 7 8 . 1 ( z h m 5 2 16 . 0s p t r t / f e m i t l l a f / e s i r t u p t u o% 0 8 o t % 0 20 0 3s p c d oe l c y c y t u d t u p t u o 0 0 = ] 0 : 1 [ x l e s0 5% ] 0 : 1 [ x l e s 0 00 5% d e h s i l b a t s e s i h c i h w , e g n a r e r u t a r e p m e t g n i t a r e p o t n e i b m a d e i f i c e p s e h t r e v o d e e t n a r a u g e r a s r e t e m a r a p l a c i r t c e l e : e t o n t e e m l l i w e c i v e d e h t . m p f l 0 0 5 n a h t r e t a e r g w o l f r i a e s r e v s n a r t d e n i a t n i a m h t i w t e k c o s t s e t a n i d e t n u o m s i e c i v e d e h t n e h w ? . s n o t i d n o c e s e h t r e d n u d e h c a e r n e e b s a h m u i r b i l i u q e l a m r e h t r e t f a s n o i t a c i f i c e p s . s n o i t i d n o c d a o l l a u q e h t i w d n a s e g a t l o v y l p p u s e m a s e h t t a s t u p t u o n e e w t e b w e k s s a d e n i f e d : 1 e t o n . s t n i o p s s o r c l a i t n e r e f f i d t u p t u o e h t t a d e r u s a e m . s t o l p e s i o n e s a h p e h t o t r e f e r e s a e l p : 2 e t o n . 5 6 d r a d n a t s c e d e j h t i w e c n a d r o c c a n i d e n i f e d s i r e t e m a r a p s i h t : 3 e t o n
idt ? / ics ? 3.3v lvpecl frequency synthesizer 6 ics843242ag rev. a november 4, 2008 ics843242 femtoclocks? crystal-to-3.3v l vpecl frequency synthesizer preliminary t ypical p hase n oise at 625mh z 625mhz rms phase jitter (random) 1.875mhz to 20mhz = 0.4ps (typical) o ffset f requency (h z ) n oise p ower dbc hz ? ? ? ethernet filter raw phase noise data phase noise result by adding an ethernet filter to raw data
idt ? / ics ? 3.3v lvpecl frequency synthesizer 7 ics843242ag rev. a november 4, 2008 ics843242 femtoclocks? crystal-to-3.3v l vpecl frequency synthesizer preliminary p arameter m easurement i nformation t pw t period t pw t period odc = x 100% qa, qb rms p hase j itter o utput s kew 3.3v c ore /3.3v o utput l oad ac t est c ircuit scope qx nqx lvpecl v ee 2v -1.3v0.165v o utput r ise /f all t ime clock outputs 20% 80% 80% 20% t r t f v sw i n g v cc , v cco_a. _b nqa, nqb o utput d uty c ycle /p ulse w idth /p eriod t sk(o) qy qx nqy nqx phase noise mas k offset frequency f 1 f 2 phase noise plot rms jitter = area under the masked phase noise plot noise power v cca 2v
idt ? / ics ? 3.3v lvpecl frequency synthesizer 8 ics843242ag rev. a november 4, 2008 ics843242 femtoclocks? crystal-to-3.3v l vpecl frequency synthesizer preliminary a pplication i nformation c rystal i nput i nterface the ics843242 has been characterized with 18pf parallel resonant crystals. the capacitor values shown in figure 2 below were determined using a 31.25mhz or 26.041666mhz f igure 2. c rystal i npu t i nterface 18pf parallel resonant crystal and were chosen to minimize the ppm error. p ower s upply f iltering t echniques as in any high speed analog circuitry, the power supply pins are vulnerable to random noise. to achieve optimum jitter per- formance, power supply isolation is required. the ics843242 provides separate power supplies to isolate any high switching noise from the outputs to the internal pll. v cc , v cca , v cco_a and v cco_b should be individually connected to the power supply plane through vias, and 0.01f bypass capacitors should be used for each pin. figure 1 illustrates this for a generic v cc pin and also shows that v cca requires that an additional10 resistor along with a 10f bypass capacitor be connected to the v cca pin. f igure 1. p ower s upply f iltering 10 v cca 10 f .01 f 3.3v .01 f v cc c1 33p x1 18pf parallel crystal c2 27p xtal_out xtal_in
idt ? / ics ? 3.3v lvpecl frequency synthesizer 9 ics843242ag rev. a november 4, 2008 ics843242 femtoclocks? crystal-to-3.3v l vpecl frequency synthesizer preliminary i nputs : c rystal i nputs for applications not requiring the use of the crystal oscillator input, both xtal_in and xtal_out can be left floating. though not required, but for additional protection, a 1k resistor can be tied from xtal_in to ground. lvcmos c ontrol p ins all control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. a 1k resistor can be used. r ecommendations for u nused i nput and o utput p ins o utputs : lvpecl o utputs all unused lvpecl outputs can be left floating. we recommend that there is no trace attached. both sides of the differential output pair should either be left floating or terminated. lvcmos to xtal i nterface the xtal_in input can accept a single-ended lvcmos signal through an ac coupling capacitor. a general interface diagram is shown in figure 3. the xtal_out pin can be left floating. the input edge rate can be as slow as 10ns. for lvcmos inputs, it is recommended that the amplitude be reduced from full swing to half swing in order to prevent signal interference with the power rail and to reduce noise. this configuration requires that the output f igure 3. g eneral d iagram for lvcmos d river to xtal i nput i nterface impedance of the driver (ro) plus the series resistance (rs) equals the transmission line impedance. in addition, matched termination at the crystal input will attenuate the signal in half. this can be done in one of two ways. first, r1 and r2 in parallel should equal the transmission line impedance. for most 50 applications, r1 and r2 can be 100 . this can also be accomplished by removing r1 and making r2 50 . r2 zo = 50 vdd ro zo = ro + rs r1 vdd xta l _ i n xta l _ o u t .1uf rs
idt ? / ics ? 3.3v lvpecl frequency synthesizer 10 ics843242ag rev. a november 4, 2008 ics843242 femtoclocks? crystal-to-3.3v l vpecl frequency synthesizer preliminary t ermination for 3.3v lvpecl o utputs v cc - 2v 50 50 rtt z o = 50 z o = 50 fout fin rtt = z o 1 ((v oh + v ol ) / (v cc ? 2)) ? 2 3.3v 125 125 84 84 z o = 50 z o = 50 fout fin the clock layout topology shown below is a typical termina- tion for lvpecl outputs. the two different layouts mentioned are recommended only as guidelines. fout and nfout are low impedance follower outputs that generate ecl/lvpecl compatible outputs. therefore, ter- minating resistors (dc current path to ground) or current sources must be used for functionality. these outputs are f igure 4b. lvpecl o utput t ermination f igure 4a. lvpecl o utput t ermination designed to drive 50 transmission lines. matched imped- ance techniques should be used to maximize operating fre- quency and minimize signal distortion. figures 4a and 4b show two different layouts which are recommended only as guidelines. other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations.
idt ? / ics ? 3.3v lvpecl frequency synthesizer 11 ics843242ag rev. a november 4, 2008 ics843242 femtoclocks? crystal-to-3.3v l vpecl frequency synthesizer preliminary figure 5 shows an example of ics843242 application schematic. in this example, the device is operated at v cc = 3.3v. the 18pf parallel resonant 25mhz crystal is used. the c1 = 27pf and c2 = 33pf are recommended for frequency accuracy. for different vcca u1 ics843242 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 nqb qb vcco_b selb1 selb0 vcco_a qa nqa fb_sel vcca vcc sela0 sela1 vee xta l _ o u t xta l _ i n ru1 1k x1 25mhz to logic input pins c2 33pf 1 8 p f vcc set logic input to '0' + - c6 0.1uf r1 133 vcco_a sela0 ru2 not install to logic input pins c5 0.1uf r3 10 vcc vcco_b r2 133 optional y-termination zo = 50 ohm vcc r7 50 set logic input to '1' vcco_b + - (u1-6) vcco_a c3 10u c1 27pf (u1-3) selb0 vcc r5 82.5 r4 82.5 3.3v sela1 rd2 1k selb1 vcc=3.3v zo = 50 ohm c4 0.01u logic control input examples fb_sel r6 50 zo = 50 ohm rd1 not install zo = 50 ohm r8 50 c7 0.1uf vcc (u1-11) board layout, the c1 and c2 may be slightly adjusted for optimizing frequency accuracy. two examples of lvpecl termination are shown in this schematic. additional termination approaches are shown in the lvpecl termination application note. s chematic l ayout f igure 5. ics843242 s chematic e xample
idt ? / ics ? 3.3v lvpecl frequency synthesizer 12 ics843242ag rev. a november 4, 2008 ics843242 femtoclocks? crystal-to-3.3v l vpecl frequency synthesizer preliminary p ower c onsiderations this section provides information on power dissipation and junction temperature for the ics843242. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the ics843242 is the sum of the core power plus the power dissipated in the load(s). the following is the power dissipation for v cc = 3.3v + 5% = 3.465v, which gives worst case results. note: please refer to section 3 for details on calculating power dissipated in the load. ? power (core) max = v cc_max * i ee_max = 3.465v * 125ma = 433mw ? power (outputs) max = 30mw/loaded output pair if all outputs are loaded, the total power is 2 * 30mw = 60mw total power _max (3.465v, with all outputs switching) = 433mw + 60mw = 493mw 2. junction temperature. junction temperature, tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. the maximum recommended junction temperature for hiperclocks tm devices is 125c. the equation for tj is as follows: tj = ja * pd_total + t a tj = junction temperature ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance ja must be used. assuming no air flow and a multi-layer board, the appropriate value is 92.4c/w per table 7 below. therefore, tj for an ambient temperature of 70c with all outputs switching is: 70c + 0.493w * 92.4c/w = 115.5c. this is below the limit of 125c. this calculation is only an example. tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow , and the type of board (single layer or multi-layer). t able 7. t hermal r esistance ja for 16- pin tssop, f orced c onvection 0 1 2.5 multi-layer pcb, jedec standard test boards 92.4c/w 88.0c/w 85.9c/w ja by velocity (meters per second)
idt ? / ics ? 3.3v lvpecl frequency synthesizer 13 ics843242ag rev. a november 4, 2008 ics843242 femtoclocks? crystal-to-3.3v l vpecl frequency synthesizer preliminary 3. calculations and equations. the purpose of this section is to derive the power dissipated into the load. lvpecl output driver circuit and termination are shown in figure 6. t o calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of v cco ? 2v. ? for logic high, v out = v oh_max = v cco_max ? 0.9v (v cco_max ? v oh_max ) = 0.9v ? for logic low, v out = v ol_max = v cco_max ? 1.7v (v cco_max ? v ol_max ) = 1.7v pd_h is power dissipation when the output drives high. pd_l is the power dissipation when the output drives low. pd_h = [(v oh_max ? (v cco_max ? 2v))/r l ] * (v cco_max ? v oh_max ) = [(2v - (v cco_max ? v oh_max )) /r l ] * (v cco_max ? v oh_max ) = [(2v ? 0.9v)/50 ] * 0.9v = 19.8mw pd_l = [(v ol_max ? (v cco_max ? 2v))/r l ] * (v cco_max ? v ol_max ) = [(2v - (v cco_max ? v ol_max )) /r l ] * (v cco_max ? v ol_max ) = [(2v ? 1.7v)/50 ] * 1.7v = 10.2mw total power dissipation per output pair = pd_h + pd_l = 30mw f igure 6. lvpecl d river c ircuit and t ermination q1 v out v cco rl 50 v cco - 2v
idt ? / ics ? 3.3v lvpecl frequency synthesizer 14 ics843242ag rev. a november 4, 2008 ics843242 femtoclocks? crystal-to-3.3v l vpecl frequency synthesizer preliminary r eliability i nformation t ransistor c ount the transistor count for ics843242 is: 3751 t able 7. ja vs . a ir f low t able for 16 l ead tssop ja by velocity (meters per second) 0 1 2.5 multi-layer pcb, jedec standard test boards 92.4c/w 88.0c/w 85.9c/w
idt ? / ics ? 3.3v lvpecl frequency synthesizer 15 ics843242ag rev. a november 4, 2008 ics843242 femtoclocks? crystal-to-3.3v l vpecl frequency synthesizer preliminary p ackage o utline - g s uffix for 16 l ead tssop t able 8. p ackage d imensions reference document: jedec publication 95, mo-153 l o b m y s s r e t e m i l l i m m u m i n i mm u m i x a m n6 1 a- -0 2 . 1 1 a5 0 . 05 1 . 0 2 a0 8 . 05 0 . 1 b9 1 . 00 3 . 0 c9 0 . 00 2 . 0 d0 9 . 40 1 . 5 ec i s a b 0 4 . 6 1 e0 3 . 40 5 . 4 ec i s a b 5 6 . 0 l5 4 . 05 7 . 0 0 8 a a a- -0 1 . 0
idt ? / ics ? 3.3v lvpecl frequency synthesizer 16 ics843242ag rev. a november 4, 2008 ics843242 femtoclocks? crystal-to-3.3v l vpecl frequency synthesizer preliminary t able 9. o rdering i nformation r e b m u n r e d r o / t r a pg n i k r a me g a k c a pg n i g a k c a p g n i p p i h se r u t a r e p m e t g a 2 4 2 3 4 8g a 2 4 2 3 4 8p o s s t d a e l 6 1e b u tc 0 7 o t c 0 t g a 2 4 2 3 4 8g a 2 4 2 3 4 8p o s s t d a e l 6 1l e e r & e p a t 0 0 5 2c 0 7 o t c 0 f l g a 2 4 2 3 4 8d b tp o s s t " e e r f - d a e l " d a e l 6 1e b u tc 0 7 o t c 0 t f l g a 2 4 2 3 4 8d b tp o s s t " e e r f - d a e l " d a e l 6 1l e e r & e p a t 0 0 5 2c 0 7 o t c 0 . t n a i l p m o c s h o r e r a d n a n o i t a r u g i f n o c e e r f - b p e h t e r a r e b m u n t r a p e h t o t x i f f u s " f l " n a h t i w d e r e d r o e r a t a h t s t r a p : e t o n while the information presented herein has been checked for both accuracy and reliability, integrated device technology, incorp orated (idt) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patents, or l icenses are implied. this product is intended for use in normal commercial applications. any other applications such as those requiring extended temperature ranges, high reliability or other extraordina ry environmental requirements are not recommended without additional processing by idt. idt reserves the right to change any circuitry or specifications without notice. idt does not authorize or w arrant any idt product for use in life support devices or critical medical instruments.
ics843242 femtoclocks? crystal-to-3.3v l vpecl frequency synthesizer preliminary innovate with idt and accelerate your future networks. contact: www.idt.com for sales 800-345-7015 (inside usa) +408-284-8200 (outside usa) fax: 408-284-2775 www.idt .com/go/contactidt for tech support netcom@idt.com +480-763-2056 corporate headquarters integrated device t echnology, inc. 6024 silver creek valley road san jose, ca 95138 united states 800-345-7015 (inside usa) +408-284-8200 (outside usa) ? 2008 integrated device technology, inc. all rights reserved. product specifications subject to change without notice. idt, th e idt logo, ics and hiperclocks are trademarks of integrated device technology, inc. accelerated thinking is a service mark of integrated device technology, inc. all other br ands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. printed in usa

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